🚀 go-pugleaf

I wanted to highlight part of Kevin's recent post, since I think
the message is often lost here. Chip architects and workstation
designers are used to throwing around hundreds of thousands of gates
like they were confetti. The PC world is NOT like that, as Compaq
learned, very painfully, in the last few years.

Compaq has proposed a protocol that can be put into a cheap ASIC
for a cost of a few dollars. SCI can't be. We need to remember
that not all problems require baroque, elegant, complicated, and
expensive solutions.

In <1993Jan11.225829.16388@twisto.eng.hou.compaq.com> leigh@croatia.eng.hou.compaq.com (Kevin Leigh) writes:

>Although much emphasis has been placed on low pin counts in 
>all of our correspondence, getting low pin counts is not a 
>sufficient cost metric.  It has been explained to us by 
>those knowedgeable about SCI that SCI implementations range 
>from 50K to 100K gates in complexity.  An Anet inteface can 
>be done with <1K gates for a simple, slave-only device (e.g. 
>a serial port controller) to around 10K gates for a multi-
>request mastering device (e.g. an FDDI controller.)  This 
>magnitude of difference is noticable no matter how 
>inexpensive one can purchase ASICs.