Article View: comp.arch
Article #12576Re: 64-bit chips, 32-bit compatibility?
From: Dan Pop
Date: Mon, 25 Sep 1995 10:18
Date: Mon, 25 Sep 1995 10:18
39 lines
2343 bytes
2343 bytes
In <jgkDFG9HJ.49x@netcom.com> Joe Keane <jgk@netcom.com> writes: >Then look at the Alpha instruction set. It has instructions for 32-bit add, >subtract, and multiply. It also has instructions for 32-bit load and store, >even though it *doesn't* have single instructions for byte load and store! >That seems just a bit peculiar for a `pure' 64-bit, byte-addressed machine. Then look at the PDP-11 instruction set. It supports both byte and word operands. That seems just a bit peculiar for a `pure' 16-bit, byte-addressed machine. >If it seems a bit ambiguous at the assembly level, look at the C interface. >For integer types, `int' is usually the `natural word size' of the machine, Hear, hear. How many C compilers for the 8080 or Z80 using an 8-bit int have you seen/used? >and it's common that `short' is a half-word, and/or `long' is a double-word. As far as I know, the concept of "word" is meaningless on Alpha. "half-word" and "double-word" even more so. The C compilers for Alpha simply assign a _standard_ type to every integer size supported by the implementation. This is precisely what the C compilers for other platforms should have done, as well, instead of stupidly assigning int and long to the same size and inventing the gratuitous long long type for 64-bit integers. >If you look at the Alpha, this scheme fits perfectly: it's a 32-bit machine. Except that it happens to have 64-bit general purpose registers and supports a 64-bit virtual address space (and much more than 4 GB of real memory), features which don't fit at all to a 32-bit machine (at least, not to any that I know of). Dan -- Dan Pop CERN, CN Division Email: Dan.Pop@mail.cern.ch Mail: CERN - PPE, Bat. 31 R-004, CH-1211 Geneve 23, Switzerland
Technical Details
Message-ID:
<danpop.812024316@rscernix>Path:
arc1-ca.pugleaf.net!CERN.ch!rscernix!danpopReferences:
<43p1g8$s24@rbdc.rbdc.com> <43srit$94b@hermes.synopsys.com> <43tada$8i6@rbdc.rbdc.com> <jgkDFG9HJ.49x@netcom.com>Show Full Headers
Complete Article Headers
Newsgroups: comp.arch,comp.lang.c Path: arc1-ca.pugleaf.net!CERN.ch!rscernix!danpop From: Dan.Pop@mail.cern.ch (Dan Pop) Subject: Re: 64-bit chips, 32-bit compatibility? X-Nntp-Posting-Host: ues5.cern.ch Message-ID: <danpop.812024316@rscernix> Keywords: word Sender: news@news.cern.ch (USENET News System) Organization: CERN European Lab for Particle Physics X-Newsreader: NN version 6.5.0 #7 (NOV) References: <43p1g8$s24@rbdc.rbdc.com> <43srit$94b@hermes.synopsys.com> <43tada$8i6@rbdc.rbdc.com> <jgkDFG9HJ.49x@netcom.com> Date: Mon, 25 Sep 1995 10:18:36 GMT