Article View: comp.arch
Article #12925Re: shared memory multiproc. question
From: crowl
Date: Mon, 02 Feb 1987 15:10
Date: Mon, 02 Feb 1987 15:10
22 lines
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1634 bytes
In article <76700001@uiucdcsp> johnson@uiucdcsp.UUCP writes:
>There are a number of shared memory multiprocessors on the market today that
>consist of a number of high-end microprocessors on a single bus.
Single bus multiprocessors tend to not scale much past 32 processors. Other
interconnection topologies scale better. The Intel Hypercube and the BBN
Butterfly scale with O(n log n) interconnection costs. Meshes and rings
scale with O(n) interconnection costs.
>Decent performance is obtained by using fancy cache technology. Making a
>single board computer is pretty trivial now-a-days, and making a
>multiprocessor system without the caches is not much harder but fairly
>pointless.
It is pointless only if you have a shared bus. The BBN Butterfly has up to
256 68000s each with local memory, but without caches. A switch handles
memory references to remote nodes.
--
Lawrence Crowl 716-275-5766 University of Rochester
crowl@rochester.arpa Computer Science Department
...!{allegra,decvax,seismo}!rochester!crowl Rochester, New York, 14627
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!watmath!clyde!rutgers!seismo!rochester!crowl From: crowl@rochester.UUCP Newsgroups: comp.arch Subject: Re: shared memory multiproc. question Message-ID: <24385@rochester.ARPA> Date: Mon, 2-Feb-87 10:10:29 EST Article-I.D.: rocheste.24385 Posted: Mon Feb 2 10:10:29 1987 Date-Received: Tue, 3-Feb-87 19:02:00 EST References: <76700001@uiucdcsp> Reply-To: crowl@rochester.UUCP (Lawrence Crowl) Organization: U of Rochester, CS Dept, Rochester, NY Lines: 22