Article View: comp.arch
Article #12989registers
From: lamaster
Date: Wed, 18 Feb 1987 01:56
Date: Wed, 18 Feb 1987 01:56
41 lines
2796 bytes
2796 bytes
>Article 348 of comp.arch:
>From: urip@orcisi.UUCP
>The conventions for saving registers by the caller vs. the callee were
>mentioned too, but no one mentioned the posibility of a compromise between
>the two - combined caller and callee save. This convention is used by
>good old Portable C Compiler (pcc). By this convention, the registers
>are divided into two groups: volatile and non-volatile registers
>(on the VAX and NS32000 the volatile registers are R0..R2 and the rest are
>non-volatile). Volatile register means that a procedure call may change
>its contents, so it has to be saved by the caller (or not used across
>procedure calls). Non-volatile register means that a procedure call is
>guaranteed to retain its old value, so it has to be saved by the callee
>(if used by the callee).
>Uri Postavsky (...utgpu!syntron!orcisi!urip)
The Cyber 205 (a machine with 256 general purpose registers) also uses this
mechanism to good effect. Library function calls use the volatile
registers. The compilers use volatile registers within expressions and
within basic block optimization, so they don't need to be saved at function
call time. Works well. There is also an instruction, used at subroutine
entry by subroutines and functions which use nonvolatile registers, to do
a multiple save on as many registers as needed, to the desired location
(module's data area, or stack, depending on the language &etc.).
With 256 registers, most scalar variables are automatically register
variables, and the number of volatile registers (about 12 I think) is
enough to take care of the temporary results of most simple scalar
functions.
Hugh LaMaster, m/s 233-9, UUCP {seismo,topaz,lll-crg}!ames!pioneer!lamaster
NASA Ames Research Center ARPA lamaster@ames-pioneer.arpa
Moffett Field, CA 94035 ARPA lamaster@pioneer.arc.nasa.gov
Phone: (415)694-6117 ARPA lamaster@ames.arc.nasa.gov
"In order to promise genuine progress, the acronym RISC should stand
for REGULAR (not reduced) instruction set computer." - Wirth
("Any opinions expressed herein are solely the responsibility of the
author and do not represent the opinions of NASA or the U.S. Government")
Technical Details
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!watmath!clyde!rutgers!lll-lcc!ames!pioneer!lamaster From: lamaster@pioneer.UUCP Newsgroups: comp.arch Subject: registers Message-ID: <336@ames.UUCP> Date: Tue, 17-Feb-87 20:56:00 EST Article-I.D.: ames.336 Posted: Tue Feb 17 20:56:00 1987 Date-Received: Thu, 19-Feb-87 05:43:01 EST Sender: usenet@ames.UUCP Reply-To: lamaster@pioneer.UUCP (Hugh LaMaster) Organization: NASA Ames Research Center, Moffett Field, Calif. Lines: 41 Keywords: registers, calling sequences, instruction sets