🚀 go-pugleaf

In article <4376@columbia.UUCP> eppstein@tom.columbia.edu (David Eppstein)
writes:
>Register window machines such as the Berkeley RISCs have been discussed
>recently in this group.  I have some questions about these architectures:

I can't answer questions 1 or  2, but:
>(3) Are there machines with both dynamic (windowed) and static (normal)
>registers?  For instance it might be useful for quick O.S. interrupts to
>use only statics and not go to the trouble of setting up a register
>window stack (which would involve lots of reads and writes moving the
>old stack completely out to memory and then back again later).  Static
>registers could also be useful for non-local variables.

The Celerity "Accel" (a.k.a. C1200, C1260) provides both types of registers.
This is because of the NCR-32 chip we use.  That chip has a RISC-like
instruction set (register to register operations, "off-line" fetch and
store, pipeline with delayed jumps, etc.) but provides a set of 16 static,
on-chip registers.  the chip also provides access to off-chip registers and
Celerity has configured 48 of those into a register stack (16 overlapped
with caller, 16 overlapped with callee, and 16 local).

Because the chip allows more and faster operations on the static registers
they are used whenever possible.  The stack registers are used mostly for
parameter passing and static register saving but they are also used for
local variables when all the static registers are allocated.

The system provides several sets (banks) of register stacks (number varies
by model) which are allocated to running processes to reduce memory saving
and restoring on process switch.  For fast OS operation the kernel just
switches to a separate bank allocated for this purpose.

Other off-chip registers have been allocated as privileged "kernel scratch
pad" registers.  These registers can be used to hold kernel information
about the executing process and are used to quickly save some of the static
registers.

						-- J. J. Whelan
						   Celerity Computing