🚀 go-pugleaf

In article <15243@sun.uucp>, klein%gravity@Sun.COM (Mike Klein) writes:
> A 40 nS cycle means 25 peak MIPS, for the case where the Am29000 is executing
> a loop of NOPs out of its on-board I cache (as one example).  Elsewhere, I saw
> it mentioned that the average (simulated) cycles per instruction on this
> machine is about 1.5 on large C programs; dividing 25 MIPS by 1.5 gives you
> 16.67 MIPS.  Neither number is a comparison against a VAX/780.
> 
> I don't see any numbers on the performance impacts of things like cache misses,
> interrupts, and the processor running an operating system.

Perhaps a small description of our simulation environment is in order.  Our
internal simulator simulates the Am29000 in conjunction with an external
memory environment, which may also include caches (both instruction and data).
The simulator is written at a very detailed level, incorporating all of the
possible pipeline stalls and exceptions (and their interactions) that may be
encountered during the execution of a program. 

The external memory model used to derive these numbers consists of separate,
64K byte instruction and data caches, which have a 2-cycle access time, with
a single-cycle burst mode interface.  Main memory has a 4-cycle (160 ns)
access with single-cycle burst for reload.  Branch target cache misses, TLB
misses and reloads, and external instruction and data cache misses were
included in the simulations.  Actually, external caches aren't required for
decent performance; we can also interface to video-DRAMS quite well.

With this simulation model, we have attempted to describe a real (i.e.
semi-easily attainable) system, instead of a "hot-box".  We have seen
real programs running at 24.5 MIPS on this system.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad)