🚀 go-pugleaf

In article <15217@amdcad.UUCP> tim@amdcad.UUCP (Tim Olson) writes:
>Perhaps a small description of our simulation environment is in order.  Our
>internal simulator simulates the Am29000 in conjunction with an external
>memory environment, which may also include caches (both instruction and data).
>The simulator is written at a very detailed level, incorporating all of the
>possible pipeline stalls and exceptions (and their interactions) that may be
>encountered during the execution of a program. 
>
>The external memory model used to derive these numbers consists of separate,
>64K byte instruction and data caches, which have a 2-cycle access time, with
>a single-cycle burst mode interface.  Main memory has a 4-cycle (160 ns)
>access with single-cycle burst for reload.  Branch target cache misses, TLB
>misses and reloads, and external instruction and data cache misses were
>included in the simulations.  Actually, external caches aren't required for
>decent performance; we can also interface to video-DRAMS quite well.

I have several questions regarding the simulation. It would
be quite unfair to compare the running times for a real VAX 11/780 against
a simulation, unless the following effects are included in the simulation:

1) Were cold start effects included? If so, how are they simulated?

2) How were page faults simulated?  Are these times included?

3) Was logic for the cache and TLB (an assumption) simulated?

4) Are the effects of I/O simulated (say 10, 25, and 50% bus bandwidth
consumed by I/O devices)? What model?

5) How are system times (I assume that UNIX is used) calculated? Is this
work done by the UNIX kernel simulated?

I don't mean to put the AM29000 down (as including all of the above into
a simulation is beyond difficult), but using simulation times to compare
performance against a real machine is unreasonable (as is a MIPS
to MIPS comparison).

Mike Shebanow
shebanow@ji.berkeley.edu