HP Precision Architecture (was Re: 64 Vs 32)

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Article #13243

#13243

From: I am NOT your Sweet Baboo
Date: Tue, 17 Mar 1987 17:25

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In article <1308@ucbcad.berkeley.edu>, faustus@ucbcad.berkeley.edu (Wayne A. Christopher) writes:
> I just read somewhere that the new HP Precision Architecture supports "up
> to 64-bit virtual addresses".  It seems to have a 32-bit internal datapath,
> however.  Can anybody explain what the 64-bit addresses are?
> 	Wayne

Like I said in the Summary, they allow (in the long run...) a 32-bit segment
number, with 32 bits address space in each segment.  They gave a
presentation here a little while ago and told us all about it.

I think they said that they didn't use the segment register for much yet,
since they didn't really need it.

Does this mean we're going have "small memory model" and "large memory
model" compilers? :-)

 - irving "just in case 4 Gbytes isn't enough" reid -
-- 
reid@sask.uucp                          {alberta, ihnp4, utcsri}!sask!reid

What the world REALLY needs is a good Automatic Bicycle Sharpenona3

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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: arc1-ca.pugleaf.net!utzoo!mnetor!seismo!lll-lcc!ptsfa!ihnp4!alberta!sask!reid
From: reid@sask.UUCP (I am NOT your Sweet Baboo)
Newsgroups: comp.arch
Subject: HP Precision Architecture (was Re: 64 Vs 32)
Message-ID: <638@sask.UUCP>
Date: Tue, 17-Mar-87 12:25:03 EST
Article-I.D.: sask.638
Posted: Tue Mar 17 12:25:03 1987
Date-Received: Sat, 21-Mar-87 03:40:31 EST
References: <3810013@nucsrl.UUCP> <1308@ucbcad.berkeley.edu>
Organization: University of Saskatchewan
Lines: 21
Summary: HP precision architecture uses segments

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