🚀 go-pugleaf

>Conversely when the system receives an interrupt/exception the address
>map is set to the current process and consequently the system
>is operating in the context of the current process, a major
>feature which does not exist on any memory managed processor
>that I'm intimately familiar with.

I'm not sure what you mean.

I presume by "...when the system receives an interrupt/exception the
address map is set to the current process..."  that you mean "when
the interrupt/exception routine is running, the 'user' half of the
address space is mapped in where you think it is", and not "when an
exception occurs the system maps the current process in"?  VAXes
don't set the address map to map in the current process; they don't
have to.

I don't know what "memory managed processor" means here.  Sun-3s
certainly have memory management hardware, although the MMU is not on
the chip, and the current process' address space is mapped in "where
you think it is"; i.e., the kernel can (and does) copy data from or
to the user's address space by using the pointer the user provides,
without any relocation.  (This is not the case on a Sun-2.)

The Motorola 68851 MMU permits you to run with the same address space
in supervisor and user mode; in such a system, presumably the
exception or interrupt handler would have the current process'
context.  According to the data sheet I have for the NS16082 (*sic* -
it's an old data sheet), it also permits you to map memory this way.

On most processors I'm familiar with, interrupt and exception
handlers run with the current process' address space mapped in
(unless the OS deliberately arranges to do things differently).
Interrupt handlers, though, usually don't care (they have no business
monkeying with whatever random process happened to be running when
the interrupt occurred); exception handlers normally do care.  What
processors are you familiar with?  Why don't interrupt or exception
handler run "in the context of" the current process on those
processors?  (Is this a function of the processor or the OS?)

>Can anyone that has the "VAX Architecture Reference Manual" handy, tell
>me if it explicitly defines the regions and the single level paging store?

It does - or, at least, the 20 May 1982 edition (Revision 6.1) does.
It explicitly indicates how addresses are translated.