🚀 go-pugleaf

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>Anyone who can tell me why these chips (1) weren't developed years ago and
>(2) aren't standard on every medium-size architecture with floating point
>deserves a beer.

HP probably has the most sophisticated versions of the CORDIC
algorithms around.  CORDIC has been used in all of the HP
calculators, and the code has been tweaked by no less than Prof.
Kahan (of IEEE FP standard fame). HP did build a CORDIC FP processor
box for their 2100 series of minicomputers, but no one bought it, so
it was dropped.

I think the main reason that no one has done a CORDIC chip is that
the hardware and datapaths required are an addition to the multiplier
and adder that the normal FP functions use. Doing it with
Taylor series adds some sequencing logic or more microcode, and I
guess that isn't nearly so bad. 

Its a tradeoff, of course. The market for high performance trig function FPUs
has got to be smaller than add/sub/mul/div, so no one has gone for the niche
market. There is also much less expertise (much less exposure) to the cordic
algorithms, and their subtleties.


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