🚀 go-pugleaf

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	This is my first posting, so if there is any mistake, please
excuse.

	I am doing a project on MMU's, and from reading various uP
data books, I have several questions:

	The Intel iAPX 286 has an on-chip  MMU.
	The Motorola 68020 has an off-chip MMU (68851).
	What are the important deciding factors in designing a MMU
on-chip or off-chip?

	Three I can think of:  execution speed, chip space, and
additional support.

	Execution Speed:  In general, on-chip MMU is faster than
off-chip MMU.

	Chip Space:  Sometimes, there is not enough space for putting
a MMU on-chip.  Sometimes, a cache is implemented instead of a MMU.

	Additional Support:  If the MMU is on-chip, then some
additional instructions might be needed.  If the MMU is off-chip, then
additional pins might be needed.

	It seems that the trend is putting the MMU on-chip.  68020 has
no on-chip MMU, but 68030 has a subset of MMU.  iAPX 386 has MMU on
chip, and so is the National Semiconductor 32532 (I haven't read the
data books yet, so I might be mistaken).  Fairchild Clipper has an
off-chip MMU.

	Question 1 :  are there any other factors that might affect the
design of the MMU being on-chip or off-chip?

	Question 2 :  if there is enough space on the chip, would
everybody put the MMU on-chip?

	Question 3 :  if there is only enough room for either a cache
or a MMU, which one will prevail?

Roy Fan  fan@cs.ucla.edu