🚀 go-pugleaf

In article <6047@ism780c.UUCP> tim@ism780c.UUCP (Tim Smith) writes:
>I read a claim somewhere that said that it is better to use the on-chip
>space for floating point, and make the MMU external, rather than have an
>on-chip MMU and an off-chip floating point unit.
>
>The argument was that you have to go off chip anyway to access memory,
>so it should be possible to make an external MMU as efficient as an
>internal one, whereas external floating point will be much slower than
>internal floating point.

1. There is no right answer, as usual.
It depends on what your priorities are, how much silicon you have,
all of the other architectural tradeoffs you've made, etc, etc,
what technology trends you're expecting to track, etc.

2.  There are a couple statements that one can make:
At the current typical state of microprocessor technology
[say, 1.2 - 2.0 micron]
	a) If you have on-chip FP, it won't be fast [remember, we think
	fast is a 2-cycle DP add or 5-cycle multiply, not 30 or 50-cycles].
	A serious micro FPU can be bigger than the CPU chip.
	[Ours certainly is!]  If we had more die area, our chippers
	would go knock out some more cycles, not cram it on the CPU.

	b) If you don't do on on-chip MMU:
		0) You can build MMUs from fast SRAMs
		OR
		1) You can have an off-chip MMU that sooner or later
		adds wait states as your systems get faster. [it's been
		interesting to see how performance of the same 16MHz 68K
		has varied according to what's around it].
		OR
		2) You will need special integrated cache-MMU parts.
		OR
		3) You will go with virtual caches, sooner or later.
	(These are not necessarily bad, but there are interesting consequences
	for system design and OS's for some of them.)
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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