🚀 go-pugleaf

In article <278@winchester.mips.UUCP>, mash@mips.UUCP (John Mashey) writes:
> 3) When publishing performance figures of microprocessors, if there is
> to be ANY semblance of credibility, you MUST specify the memory system
> hooked to the micro as modeled in the simulations, and give other environmental
> issues.  Here is a starting list:
> 	cache size(s)
> 	data cache nature: write-thru [maybe with write buffers],
> 		or write-back
> 	cache line sizes
> 	number of cycles penalty for refilling the caches, refill nature
> 	main memory DRAM speed used in the model to achieve the above.
> 	environment: standalone, or in simulated virtual memory environment,
> 	including MMU overhead, if any, and something for OS overhead
> 	[like clock ticks that execute code that trashes the caches
> 	now and then].
> [A bunch of this is very relevant to what real performance one will see
> the list some real machine numbers, that following the usual Dhrystone

I may get corrected on this shortly.  I believe that the simulations were
done with the assumptions that external memory was all 0 wait state.

However, in support of this let me say that we have a parallel design effort
on a vme board pair that supports a 64K direct mapped cache, write
through with a write buffer.  The cache is organized as 4096 lines of 
16 bytes.  The board also has 4 Meg of on-board ram.

In this configuration, our simulations show that the board with the 532
will be able to sustain a performance of approximately 95% of the
full rated performance of the 532.  Not bad, and one doesn't need to
pay mega bucks for the RAM.

Roger Thompson