🚀 go-pugleaf

> When reading the data sheet I noticed that the TLB entries
> don not have any "page used" flag nor any "page modified"
> flag. Does that mean that the AM29000 memory managenent is even
> more crippled than on a VAX (which doesn't have a "page used" flag???

Sounds reasonable.  MIPSCo did this too.  The result isn't "crippled",
because it takes a fair bit of hardware to add those flags and they don't
buy you very much over a software simulation.  For real programs, on a
given page each of those flags is either constantly on or rarely on,
meaning that the software-simulation overhead is quite low.  Notice that
not implementing the flags means that TLB entries never have to be written
back to main memory when they are replaced in the TLB, which makes TLB
management simpler and quicker.  On the whole, it's a win.  I looked at
TLB management a little bit a while ago, and formed a strong suspicion
that software simulation was actually the way to go even when the hardware
*does* support the flags!  (Software simulation is more flexible.)

> On TLB misses, as far as I understand, a software trap is generated.
> Are there any figures on typical interrupt routine times for handling
> the misses? What is the performance penalty, compared to miss
> handling in hardware?

Dunno about the AMD machine, but MIPSCo cited typical TLB-miss-handling
times in software (they do that too) substantially *shorter* than the
VAX 780's hardware times.  Given careful design, there need be little
penalty.
-- 
"If you want PL/I, you know       Henry Spencer @ U of Toronto Zoology
where to find it." -- DMR         {allegra,ihnp4,decvax,pyramid}!utzoo!henry