Article View: comp.arch
Article #1381Re: MIPS, SPARK, RISC, and CISC
From: Robert Cousins
Date: Fri, 30 Jun 1989 13:45
Date: Fri, 30 Jun 1989 13:45
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1573 bytes
In article <3536@hplabsz.HPL.HP.COM> kjchang@hplabsz.UUCP (Jeng Chang) writes: >I have a couple of questions and I hope someone can enlighten me: >3. RISC. I knew this was a berkeley stuff. Does Stanford have a similar > stuff? The original RISC processors were experiemental and developed independently (more or less) at 1BM, Berkeley and Standford. Today's RISC processors, such as the 88K, define a complete yet general purpose architecture suitable for a wide variety of tasks. These original attempts were designed more for proof of purpose than anything else. >4. CISC. What is its fate? Can I get some good articles on this topic > which are not written by berkeley's risc group |-)? CISC is going strong and most marketing studies show that CISC processors will continue to dominate the market for atleast the next few years. However, if you read the marketing hype you will notice that CISCs are becomming RISCier with each generation. >Thanks for your attention, >-Chang >e-mail: kjchang@hplkjc.hpl.hp.com or > kjchang@hplabsz.hpl.hp.com Robert Cousins Dept. Mgr., Workstation Dev't. Data General Corp. Speaking for myself alone.
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!uunet!dg!rec From: rec@dg.dg.com (Robert Cousins) Newsgroups: comp.arch Subject: Re: MIPS, SPARK, RISC, and CISC Message-ID: <198@dg.dg.com> Date: 30 Jun 89 13:45:28 GMT References: <3536@hplabsz.HPL.HP.COM> Reply-To: uunet!dg!rec (Robert Cousins) Organization: Data General, Westboro, MA. Lines: 30