🚀 go-pugleaf

In article <2203@taux01.UUCP> cjosta@tasu77.UUCP (Jonathan Sweedler) writes:
>impression that RISC machines need more complex compilers, not just
>because of the need for more optimization, but because RISC chips are
>'dumber' than CISC chips...
>This means that interlocks must be handled in the compiler.  So
>forgetting about all optimization, just writing a compiler that WORKS
>on a RISC chip is by DEFINITION harder than writing a compiler for a
>CISC chip.

Not necessarily.  The winner of the 'dumb compiler that works' award
goes to one that just puts nop's anywhere that could have a problem; 
after loads, in branch delay slots...

>Correct me if I'm wrong, but I remember looking at some of the initial
>specs for the Intel 860 and that thing looked like a nightmare to write
>a compiler for.  Forget about optimizations, just getting floating
>point results out of the FP pipeline, requires that the compiler have
>knowledge of the internals of the hardware.

This is true, and makes me believe that IEEE FP and RISC are
incompatible.  Both major implementations (860 and 88000 (I'm glad I
can admit knowlege of the 88000 now)) show that this force-fit causes
problems.  By RISC arguments, let sw handle the exceptions.  But IEEE
FP has so many exceptions by its over-complex nature that [not the
compiler really, the OS] absolutely must be able to handle said
hardware internals, and must do it efficiently; underflow happens
more often than you think.
-Stan