Code scheduling (was instruction reordering is difficult)

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Article #1637

#1637

From: rajeev chandrasekhar
Date: Sun, 23 Jul 1989 17:52

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i was wondering if anybody had any numbers to show performance improvements
after code reordering .... i want to get a feel for what impact scheduling
has on overhaul performance for "CISC" and "RISC" processors....

thanks.
rajeev

<disclaimer: i speak simply for myself..>

Rajeev Chandrasekhar
Intel Corp            >> theres someone in my head, and its not me << 
2625, Walsh Ave MS SC4-59                      (408) 765-4632
Santa Clara, CA 95051  {hplabs,oliveb}!intelca!mipos2!rajeevc

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!oliveb!mipos3!mipos2.intel.com!rajeevc
From: rajeevc@mipos2.intel.com (rajeev chandrasekhar)
Newsgroups: comp.arch
Subject: Code scheduling (was instruction reordering is difficult)
Message-ID: <526@mipos3.intel.com>
Date: 23 Jul 89 17:52:55 GMT
Sender: news@mipos3.intel.com
Reply-To: rajeevc@mipos2.intel.com (rajeev chandrasekhar)
Organization: Microprocessor Component Group, Intel Corp., Santa Clara, CA
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