🚀 go-pugleaf

In article <23802@winchester.mips.COM>, mash@mips.COM (John Mashey) writes:
> 2) It is clear that code reordering varies in usefulness from architecture
> to architecture, BUT the boundary is not RISC-vs-CISC, but determined
> by presence or absence of various features and the ways compilers use them.
> In general, any machine with nontrivial pipelines and/or separate
> functional units may well benefit.  Note that CDCs did all this years ago.  
> Also, I heard long ago that people were able to get >5% improvement
> on S/370-architecture systems by code-reordering.  Maybe somebody has
> a reference.  Also, maybe somebody from Amdahl or IBM would care to
> offer some inforomation on what the pipelines and functional units
> look like on their current products, because I'd suspect there are places
> where code rearrangement is usable.
> I'd strongly suspect that most machines that could execute:
> 	load	reg1,a
> 	load	reg2,b
> 	add	reg1,20
> 	sub	reg2,30
> are better off doing it that way than the following:
> 	load	reg1,a
> 	add	reg1,20
> 	load	reg2,b
> 	sub	reg2,30
> because most machines will stall on the add/sub more on the second case.

Some experiments have been conducted here at Amdahl wrt code reordering.
Fairly simple code rearrangement have produced approx. 5% improvement in
execution speed.

Current Amdahl machines have 5 or 6 stage pipelines
depending on the model.  Although the machines are microcoded
most instructions take just one flow down the pipeline.
The microcoded approach does not impact the cycle time (10ns) because
the cycle time is determined mostly by the cache access latency.
If data is in the cache, execution proceeds without delay.
Access to cache and to registers takes the same amount of time,
although a Register-Register architecture would probably allow a
shorter pipe.

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Sam Fuller / Amdahl System Performance Architecture

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