🚀 go-pugleaf

> In article <2620@cbnewsh.ATT.COM> daw@cbnewsh.ATT.COM (David Wolverton) writes:
> >This chip is in the newest AT&T 3B2 models, but I don't think the production
> >assembler supports this feature of the WE32206.

to which Greg Frazier writes:

In article <26067@shemp.CS.UCLA.EDU>, frazier@oahu.cs.ucla.edu (Greg Frazier) writes:
> ...  ATT, on the
> other hand, has an FP accelerator which supports these
> rounding modes, but it is only used in a processor whose
> machine language doesn't support them - the exact problem
> everybody's been complaining about!  Some bubble-burster
> you are... :-)

Well, to be picky, I said the "assembler" didn't support them.  The machine
language of the WE32x00 CPUs does support the rounding feature.  To get
the production assembler to "do the right thing," you would have to generate
the floating point instructions using a somewhat less mnemonic alternate
interface.  I.e. instead of the
	mfaddd.rz	%f0,%f1,%f2
instruction described in my previous note, you'd have to do something like
	SPOPD	ADD|F0SRC|F1SRC|F2DST|RZ
with approprite macro definitions for ADD, F0SRC, etc.  BTW, SPOPD
stands for Support Processor OPeration, Double precision.

And all this is true for a chip that has been commercially available in the
US for at least 2 years.

Dave Wolverton
daw@attunix.att.com