Article View: comp.arch
Article #1712delayed branch
From: David Deitcher
Date: Sun, 30 Jul 1989 07:22
Date: Sun, 30 Jul 1989 07:22
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"Delayed branch" is a technique used by RISC machines to make use of the
extra cycle needed to calculate branch targets. The compiler will put
an instruction after the branch to be executed by the CPU while the
branch target is being calculated. Does anyone have information as to
how often the compiler is able to put a useful instruction after the
branch as opposed to filling it with a NOP?
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David Deitcher (National Semiconductor Israel)
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arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!bionet!apple!voder!nsc!taux01!tasu76!cdddtaShow Full Headers
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!bionet!apple!voder!nsc!taux01!tasu76!cdddta From: cdddta@tasu76.UUCP (David Deitcher) Newsgroups: comp.arch Subject: delayed branch Message-ID: <2246@taux01.UUCP> Date: 30 Jul 89 07:22:11 GMT Sender: netnews@taux01.UUCP Reply-To: cdddta@tasu76.UUCP (David Deitcher) Organization: National Semiconductor (IC) Ltd, Israel Lines: 11