Article View: comp.arch
Article #1721Re: RISCs Register sets and PDP 10/20s
From: cliff click
Date: Tue, 01 Aug 1989 11:56
Date: Tue, 01 Aug 1989 11:56
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1426 bytes
In article <43445@bbn.COM>, slackey@bbn.com (Stan Lackey) writes: > The TI 990/9900 did this - the CPU had a 'workspace pointer' which > pointed to R0, the base of the register file, hopefully in a section > of main memory that was implemented in Schottky RAM. Thus, a context > > This would be tough to get performance, because you need real fast Doesn't TI still make/market this chip? I thought the later versions implemented the registers as a write-thru cache (bleed-thru??) - they were just as fast a "normal" registers otherwise. On a context switch you just swapped the 'workspace pointer' and the cache mechanism loaded registers as needed (and saved as needed). I thought it was a good chip that never caught on because TI can't market (at least not like *BM & *ntel). -- Cliff Click, Software Contractor at Large Business: uunet.uu.net!ficc!cliff, cliff@ficc.uu.net, +1 713 274 5368 (w). Disclaimer: lost in the vortices of nilspace... +1 713 568 3460 (h).
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arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!bionet!apple!sun-barr!texsun!texbell!sugar!ficc!cliffReferences:
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!bionet!apple!sun-barr!texsun!texbell!sugar!ficc!cliff From: cliff@ficc.uu.net (cliff click) Newsgroups: comp.arch Subject: Re: RISCs Register sets and PDP 10/20s Summary: TI99xx Message-ID: <5400@ficc.uu.net> Date: 1 Aug 89 11:56:34 GMT References: <550@augean.OZ> <43445@bbn.COM> Organization: Ferranti International Controls Lines: 18