Article View: comp.arch
Article #1738Re: FPU chip set
From: Michael Z Slater
Date: Thu, 03 Aug 1989 06:36
Date: Thu, 03 Aug 1989 06:36
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>Could this perhaps refer to the recent MECL implementation of the SPARC >architecture, as recently reported in (I think) Electronic Design? > >Now that there's an 80Mhz (I think it was) SPARC out, how is the Prisma >chip going to find a market niche? "The Prisma chip" is not a chip by a long shot. Prisma is building a GaAs minisupercomputer, whose cpu will be hundreds (possibly thousands) of chips. It happens to use the SPARC architecture (for software availability), but is in no sense a SPARC chip. GaAs isn't there yet; maybe someone else can give an estimate of how long it will be before GaAs chips of several hundred thousands transistors are practical. Prisma's systems, by the way, will be priced in hundreds of thousands of dollars. Michael Slater, Microprocessor Report mslater@cup.portal.com 550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!sun-barr!cs.utexas.edu!uunet!portal!cup.portal.com!mslater From: mslater@cup.portal.com (Michael Z Slater) Newsgroups: comp.arch Subject: Re: FPU chip set Message-ID: <20981@cup.portal.com> Date: 3 Aug 89 06:36:49 GMT References: <871@stag.UUCP> <GRUNWALD.89Jun17210544@flute.cs.uiuc.edu> Organization: The Portal System (TM) Lines: 16