🚀 go-pugleaf

In article <2284@yogi.oakhill.UUCP> cs.utexas.edu!oakhill!marvin (Marvin Denman) writes:
>
>The 88100 does have a separate adder for branches like most other chips with
>delayed branching, but the User's Manual explicitly states that for future
>compatibility the delay slot instruction cannot be a trap, jump, branch, or
>any other instruction that modifies the instruction pointer.  In other words
>this behavior, while it may be useful for at least one special case 
>application, is not guaranteed to work the same on all implementations of the
>architecture.  This allows the possibility of different pipelining schemes in
>the future without unduly tying the architect's hands.
>

The Intel i860 has the similar restrictions.