Article View: comp.arch
Article #1869Re: Vectorizing division in a do loop
From: John D. McCalpin
Date: Thu, 17 Aug 1989 21:55
Date: Thu, 17 Aug 1989 21:55
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2576 bytes
In the above referenced message, Hugh ??? <gsg0384@uxa.cso.uiuc.edu> writes:
>I've heard that vector machines are more expensive than multi-cpu parallel
>machines. I've got two questions about vector machines.
There is no reason, in principle, why this should be true.
However, almost all of the machines designed around vector pipelines
are quite expensive, while there are a fair number of parallel
boxes becoming available.
This may change if Ardent and/or Stellar make any headway in the
workstation market.
>1. For compiler design, I think vector machine architecture is easier.
> Is this true?
For operations that map onto the vector hardware, this is likely to
be true. There is also considerably more experience in the industry
at vectorizing scientific codes than parallelizing them. One of
the reasons for this is that "vectorizing" means basically one thing,
while "parallelizing" means many different things depending on the
model (MIND or SIMD), the size of the pieces, the communication
and synchronization options, etc.....
>2. Our machine is Ardent Titan. Each cpu has 64-register length vector
> registers. The problem is that this machine does not vectorize do loops
> with division. How much harder is to implement division than the other
> three operations, + - x? Is this a hardware limitation?
The Ardent Titan uses the Weitek 2264/2265 pipelined floating-point
adder and multiplier chips. Divide is not implemented in the hardware,
but is iterated using one or both of the chips (I don't remember
which way Ardent does it).
Pipelined divide units are not likely to be found on anything in
the Titan's price range.
>I'd rather have a vector machine than a multi-cpu parallel machine for
>my application. I just want more people in computer industries to pay
>more attention to vector machines.
I'll second that motion!
--
John D. McCalpin - mccalpin@masig1.ocean.fsu.edu - mccalpin@nu.cs.fsu.edu
mccalpin@delocn.udel.edu
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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!cs.utexas.edu!tut.cis.ohio-state.edu!purdue!gatech!uflorida!stat!stat.fsu.edu!mccalpin From: mccalpin@masig3.ocean.fsu.edu (John D. McCalpin) Newsgroups: comp.arch Subject: Re: Vectorizing division in a do loop Message-ID: <MCCALPIN.89Aug17175558@masig3.ocean.fsu.edu> Date: 17 Aug 89 21:55:58 GMT References: <112400003@uxa.cso.uiuc.edu> Sender: news@stat.fsu.edu Organization: Supercomputer Computations Research Institute Lines: 44