🚀 go-pugleaf

>	Cache is, by definition, a compromise.  If you really want to build
>a "no compromise" machine, make the entire main memory out of SRAM fast
>enough to keep up with the CPU.
>-- 
>Roy Smith, Public Health Research Institute
>455 First Avenue, New York, NY 10016
>{att,philabs,cmcl2,rutgers,hombre}!phri!roy -or- roy@alanine.phri.nyu.edu


Now, then, what about these fast new DRAMs?

IBM announced a 16ns part, followed by Hitachi announcing a 20ns part.
I believe that they were reasonably large (1 Mbit -- I just left the
latest of a series of articles at home).

Apparently this big jump up in DRAM performance is attained by just doing
things the sensible, brute-force way --- no more multiplexed lines, plus
a bit of bipolar on the CMOS memory chip for drivers.

Anyone have more details?  Anyone care to speculate on what faster DRAMs
will do for computer architecture?  Has anyone run simulations, either
hardware (faster DRAMs let me do away with cache), or, probably more important,
economic (fast DRAMs with lotsa pins will ride the technology curve down 
1 yr? 2 yrs? behind regular DRAMs)?

--
Andy "Krazy" Glew,  Motorola MCD,    	    	    aglew@urbana.mcd.mot.com
1101 E. University, Urbana, IL 61801, USA.          {uunet!,}uiucuxc!udc!aglew
   
My opinions are my own; I indicate my company only so that the reader
may account for any possible bias I may have towards our products.