🚀 go-pugleaf

From article <AGLEW.89Aug21205533@chant.urbana.mcd.mot.com>, by aglew@urbana.mcd.mot.com (Andy-Krazy-Glew):
> Now, then, what about these fast new DRAMs?
> 
> IBM announced a 16ns part, followed by Hitachi announcing a 20ns part.
> I believe that they were reasonably large (1 Mbit -- I just left the
> latest of a series of articles at home).
> 
> Apparently this big jump up in DRAM performance is attained by just doing
> things the sensible, brute-force way --- no more multiplexed lines, plus
> a bit of bipolar on the CMOS memory chip for drivers.
> 
> Anyone have more details?  Anyone care to speculate on what faster DRAMs
> will do for computer architecture?  Has anyone run simulations, either
> hardware (faster DRAMs let me do away with cache), or, probably more important,
> economic (fast DRAMs with lotsa pins will ride the technology curve down 
> 1 yr? 2 yrs? behind regular DRAMs)?

In particular, I haven't seen anything in the press yet about the *cycle* time,
only figures on access time.  DRAMs have always had cycle times much longer
than access times, mainly to write back the bits that were read and recharge
everything.  At least in the recent technology of 100ns access and 200 or
250ns cycle, it's often the cycle time that limits what can be done with the
memory system.

Anyone have the figures?

Another point about caches is that many fast RISC systems, such as Apollo's
DN10000 and the forthcoming Fujitsu SPARC-H, use separate instruction and data
caches to accomplish two memory operations in one cycle (so-called "Harvard
architecture").  You can't do that without caches unless you want to keep two
copies of main memory.
-- 
Michael Butts, Research Engineer       KC7IT           503-626-1302
Mentor Graphics Corp., 8500 SW Creekside Place, Beaverton, OR 97005
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Opinions are my own, not necessarily those of Mentor Graphics Corp.