🚀 go-pugleaf

In article <1989Aug24.215104.156@mentor.com> mbutts@mentor.com (Mike Butts) writes:
>
>Another point about caches is that many fast RISC systems, such as Apollo's
>DN10000 and the forthcoming Fujitsu SPARC-H, use separate instruction and data
>caches to accomplish two memory operations in one cycle (so-called "Harvard
>architecture").  You can't do that without caches unless you want to keep two
>copies of main memory.

Not two copies of main memory, just one copy of multi-ported
interleaved main memory.  One data port, one instruction port.
(While your at it, add an i/o port or two, what the hell.)
You will occasionally get a conflict, depending on the degree
of interleaving.  Of course, this isn't necessarily cheaper than
caches, certainly not as fast, and can only be justified cost-wise
with very large memories.

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Dave Christie
My opinions only, of course.