🚀 go-pugleaf

In article <208@intelca.intel.com> clif@intelca.intel.com (Ken Shoemaker) writes:
>The following information is taken from the i860 TM 64-Bit Microprocessor
>data sheet order number 240296-001.  I hope that this posting does not
>generate a meta-discussion about appropriateness of the posting....

Appropriate posting; thanx; it's much better than seeing random rumors and
misinformation, and there's plenty of technical content.

There a few questions though: I suspect this was just an oversight,
as somebody MUST know the answers, but 2 of the numbers need clarification,
or they are almost meaningless:

>Measured Performance with Current Compilers
I assume this was measured on real hardware, so are you allowed to say what
the memory system looks like?  i.e., read latency and write retirement rates,
for example?  (of course, for these particular benchmarks it probably doesn't
matter too much, since their cache miss rates are neglible :-)

>	- 24 Megawhetsones (40 MHz)
		1)  Was this single precision or double precision?
		2)  Whichever it was, what was the other one?
>	- 83K Dhrystones (40 MHz)
		1) Which version: 1.1 or 2.1?
			I assume this wasn't 1.0, whose numbers are 15% better
			than 1.1.
		2) What level of optimization?
			any inlining?
			any unusual options? (like, for example: the manual
			shows normal use of a frame pointer, which costs
			4 cycle/call, but could be suppressed if you know
			things like alloca won't be used.  Since a typical
			32-bit RISC would use 30-40 cycles/call, suppressing
			the fp-manipulation gains about 10%.)
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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