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Article #20234Re: i860 overview (long)
From: Peter da Silva
Date: Wed, 08 Mar 1989 11:56
Date: Wed, 08 Mar 1989 11:56
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In article <13322@steinmetz.ge.com>, davidsen@steinmetz.ge.com (William E. Davidsen Jr) writes: > One problem with any chip which requires alligned data is that > performance suffers when addressing bytes, to the point that a program > may become impractical. I guess I'm a bit dense today, but why? Takes the same amount of work to fetch <x> bits over an <n> x <x> bit-wide bus either way. Are you confusing alignment requirements with word addressing? After all, I don't recall the PDP-11 or 68000 having problems dealing with bytes. At best you lose a little data compression... -- Peter da Silva, Xenix Support, Ferranti International Controls Corporation. Business: uunet.uu.net!ficc!peter, peter@ficc.uu.net, +1 713 274 5180. Personal: ...!texbell!sugar!peter, peter@sugar.hackercorp.com.
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!bellcore!texbell!uhnix1!sugar!ficc!peter From: peter@ficc.uu.net (Peter da Silva) Newsgroups: comp.arch,comp.sys.intel Subject: Re: i860 overview (long) Message-ID: <3339@ficc.uu.net> Date: 8 Mar 89 11:56:28 GMT References: <807@microsoft.UUCP> <92634@sun.uucp> <13322@steinmetz.ge.com> Organization: Xenix Support Lines: 16