🚀 go-pugleaf

>> So where did Intel get the extra 22% ?
>Intel has a 64-bit bus, MIPS 32 bits.  It will take two clocks for MIPS to load
>an immediate value.  Intel can do it in one clock.  If 22% of the instruction
>mix involves immediate values, then we know where Intel 'got it.'

Unless I am missing something, Intel cannot "do it in one clock."  The
mechanism used by the i860 is essentially the same as on other RISCs:
load the low 16 bits, then overload (or add) the high 16 bits.   Even in
dual instruction mode, it takes two instructions (and usually, cycles).

>anybody remember the newsletter DTACK Grounded ?
Yes, I do.  This is the newletter that printed the *WORST* (most inaccurate)
assesment of RISC that I have yet read.  However, I think it was a letter
from a reader, and so doesn't necessarily represent the newsletter's position.