🚀 go-pugleaf

In looking thru this document, I was curious about the description
of the simulation vehicle. (page 10).  The benchmarked machine
says: 5 wait-states for first read from idle, 2 for write from idle,
zero waits for page mode read/write.
The simulation says: "Zero-wait-state memory accesses are assumed".

is that a typo, or does it really mean a perfect zero-overhead memory
system?  [we'd like to know the part number of the RAMs used to
build that memory; we'd like to buy a whole bunch of them.
Our LINPACK's are over in the corner whining that if the neighbors
get some, they want them, too . :-)]

One of the reasons for asking, of course, is that of the 4 benchmarks
[Dhrystone, Stanford, Whetstone, Linpack], 2 (S & L) were simulated, and 2
were run, although as somebody already posted, it appears that
Dhrystone was written in FORTRAN, so that number is not directly
comparable.  That leaves Whetstones.  I am a little curious that
the simulated Whetstones are LOWER than the measured Whetsones.
Although Whetstone would fit in the i860's caches pretty well,
it still seems odd that the measured number would be better, given
the assumptions described.  (There are often simplifying assumptions
built into simulators that cause +/- a few percent variations, when
simulating a program that has nontrivial kernel interactions, but
none of these are like that.)

Can anybody shed any light on these?
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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