Article View: comp.arch
Article #20286Re: i860 CPU information
From: John Mashey
Date: Tue, 14 Mar 1989 06:23
Date: Tue, 14 Mar 1989 06:23
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1887 bytes
In article <3024@alliant.Alliant.COM> jeff@alliant.Alliant.COM (Jeff Collins) writes:
......
>:There are policies that do not require this feature at all.
....
> Actually never mind that, how do you switch a process from one
> processor to another (I don't count flushing the D-cache on
> each context switch as a viable answer)?
As I posted in <15016@winchester>, you have to flush the caches
on context-switch in a single CPU, much less a multiprocessor.
As the details of the i860 become clearer, it seems obvious that
the Intel engineers designed it as a very powerful numerics coprocessor,
(and at least the Intel engineers we know say so, also)
and all the tradeoffs were made in that direction. Another way to
put it is that all the design tradeoffs one sees cry out "mini-super"-
style design (not supermini or mainframe-style).
I'm hardly privy
to the internal decisions, but it wouldn't surprise me if it hadn't
been "redesigned" (i.e. relabeled) by marketing very late in the game
to become a general-purpose chip, for such things as multi-user systems.:-)
But don't zing the engineers too much....
--
-john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!apple!vsi1!wyse!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: i860 CPU information Keywords: i860 N10 Message-ID: <15213@winchester.mips.COM> Date: 14 Mar 89 06:23:18 GMT References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM> Reply-To: mash@mips.COM (John Mashey) Distribution: usa Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 27