Article View: comp.arch
Article #20324Re: i860 CPU information
From: John Mashey
Date: Thu, 16 Mar 1989 02:51
Date: Thu, 16 Mar 1989 02:51
23 lines
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1547 bytes
In article <706@m3.mfci.UUCP> rodman@mfci.UUCP (Paul Rodman) writes:
>In article <15213@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>>As I posted in <15016@winchester>, you have to flush the caches
>>on context-switch in a single CPU, much less a multiprocessor.
>>
>
>Hmmmm. I'm not sure I understand this, I haven't read your posting
>so forgive my ignorance here.
...Description of classic process-tagged cache, etc...
The <15016@winchester> posting was a discussion of the i860
mechanism. There are, of course, numerous ways to avoid cache flushes
per context-switch or more often, even with virtual caches. I probably
should have written the following:
"on context-switch in a single i860, much less a multiprocessor i860."
--
-john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc>
UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com
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arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!rutgers!apple!vsi1!wyse!mips!mashReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!rutgers!apple!vsi1!wyse!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: i860 CPU information Keywords: i860 N10 Message-ID: <15339@winchester.mips.COM> Date: 16 Mar 89 02:51:44 GMT References: <1895@oakhill.UUCP> <21570@shemp.CS.UCLA.EDU> <3024@alliant.Alliant.COM> <15213@winchester.mips.COM> <706@m3.mfci.UUCP> Reply-To: mash@mips.COM (John Mashey) Distribution: usa Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 23