Article View: comp.arch
Article #20335Re: Virtual caches & PIDs [was Re: i860 CPU information]
From: doug carmean
Date: Thu, 16 Mar 1989 18:00
Date: Thu, 16 Mar 1989 18:00
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In article <24869@amdcad.AMD.COM> tim@amd.com (Tim Olson) asks: >Has anyone tried to use virtual, copy-back caches with PIDs to prevent >flushing like the i860 requires? Problems of how to save modified data, >as well as the consistency of shared memory come to mind... . Cypress will be offering two parts that both implement a virtual, copy-back cache with context numbers. The CY7C604 supports 4096 contexts in an on chip 2K tag. The '605 will be a multiprocessing version of the '604 which will have both virtual and physical tags to support bus snooping. Note that both parts support both copy-back and write through policies. -- -doug carmean -ROSS Technology, 7748 Hwy 290 West Suite 400, Austin, TX 78736 -ross!doug@cs.utexas.edu
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!loyola!ross!doug From: doug@ross.UUCP (doug carmean) Newsgroups: comp.arch Subject: Re: Virtual caches & PIDs [was Re: i860 CPU information] Message-ID: <223@ross.UUCP> Date: 16 Mar 89 18:00:30 GMT References: <24869@amdcad.AMD.COM> Reply-To: doug@ross.UUCP (doug carmean) Organization: ROSS Technology. Austin, TX Lines: 14