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Article #20356

interrupt handling

#20356
From: Henry Spencer
Date: Sat, 18 Mar 1989 23:38
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In article <28200290@mcdurb> aglew@mcdurb.Urbana.Gould.COM writes:
>... applying RISC principles to the hardware that would be needed to do
>something like this, I often arrive at the conclusion that a 
>simple single entry point first level handler is all that is appropriate.

Note that the MIPS machines, as I recall, vector one or two crucial
things -- user-mode TLB misses in particular -- and just run everything
else through a single entry point.  If you want full vectoring, the
software can (and probably does) do it.  Why bother doing it in hardware?
-- 
Welcome to Mars!  Your         |     Henry Spencer at U of Toronto Zoology
passport and visa, comrade?    | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
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Message-ID: <1989Mar18.233819.28542@utzoo.uucp>
Path: arc1-ca.pugleaf.net!utzoo!henry
References: <1552@vicom.COM> <28200290@mcdurb>

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Newsgroups: comp.arch
Path: arc1-ca.pugleaf.net!utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: interrupt handling
Message-ID: <1989Mar18.233819.28542@utzoo.uucp>
Organization: U of Toronto Zoology
References: <1552@vicom.COM> <28200290@mcdurb>
Date: Sat, 18 Mar 89 23:38:19 GMT