🚀 go-pugleaf

Optimization in VLSI CAD is also a black-hole for integer CPU cycles.
The problem of translating a logic design into a chip is so
complicated that it has been broken into 6 steps, most/all of which
are NP-Hard.  Some of the algorithms that can really eat your lunch
are:

1.  PLA/Logic minimization (exact solution of NP-Hard problems)
2.  Simulated Annealing / Neural Net optimization of the floorplan
    design, layout, and (global/channel) routing.  Or other types of
    iterative branch & bound algorithms for solving these problems
    optimally or even sub-optimally.

In other words, just about everything having to do with silicon
compiler "optimal chip generation" is expensive.