🚀 go-pugleaf

An idea:

Suppose every machine instruction for some hypothetical machine were of 
the form <load/store op><non-load/store op> Ra, Rb, Rc, Rx, Ry, Rz, where
Ra is the source/destination of a load/store, Rb is a base address, Rc is
an optional index, Rx is the destination of some operation (e.g., addition)
and Ry and Rz are operands.  For example:

LD.B/AND.L R1, (R2), (R3), R4, R4, R5; R1.B := *(R2 + R3), R4.L &= R5.L

Such instructions name six registers.  If there are 32 (visible) registers,
then 30 bits are required per instruction just to specify all the registers.
If all instructions were...say...forty eight bits long, then this machine
should achieve 25% more work per instruction bit than conventional RISCs.
If the machine fetches 48 bits of instruction per cycle, and can execute 
both the load/store and register-data operations in one cycle, then it
also gets UP TO twice as much work done per cycle as conventional RISCs.
Since the ALU operations and the data access function can easily be made
to operate in parallel, executing such instructions in once cycle should 
not be difficult.

Given the frequency of load/store operations, this could be a very big win.

Comments? 

Alan Lovejoy; alan@pdn; 813-530-2211; AT&T Paradyne: 8550 Ulmerton, Largo, FL.
Disclaimer: I do not speak for AT&T Paradyne.  They do not speak for me. 
__American Investment Deficiency Syndrome => No resistance to foreign invasion.
Motto: If nanomachines will be able to reconstruct you, YOU AREN'T DEAD YET.