🚀 go-pugleaf

In article <6417@cbmvax.UUCP> jesup@cbmvax.UUCP (Randell Jesup) writes:
>In article <13404@steinmetz.ge.com> davidsen@crdos1.UUCP (bill davidsen) writes:
>>  There will continue to be a demand for processors with a very high
>>instruction rate (call them RISC if you will), and also for processors
>>which will perform a given task faster with limited memory bandwidth.
>
>	Quite true.  Not everyone designs workstations bought solely by
>larger corporations.  There is _signifigant_ demand for CPUs that are
>a) fairly cheap - say current '030/881 (16MHz) pricing, and b) do the
>most _work_ given a specific memory bandwidth, determined by the speed of
>jelly-bean memory parts - say 100-120ns currently, and without expensive
>external caches.
>
>	You could sell a lot of CPUs like that.

Funny you should mention that. National Semiconductor has just announced
a new processor for the Embedded market. This is the NS32GX32.
It has the NS32532 pipeline core and the same performance 
(18,335 d/s, 8 to 10 vax mips average at 30 MHZ).
The processor is *cheap* both in actual chip cost (for pricing you will need
to contact marketing...), and what is more important, in system cost.

System cost is minimized by providing the system a very simple 
interface (non multiplexed address and data bus, one of each), 
a harvard architecture which is *ON* chip (why burden the designer
with our problems), two on-chip caches (1K data cache, 0.5K instruction cache),
code density which is second to none, dynamic bus sizing for peripherals
and boot ROMs, long address to ready timing, long address to data timing, etc.
All this provides for a CPU which is very insensitive to wait states. 
We have a system which was designed with a single bank of DRAM (no interleave)
which provides the CPU with 2 wait states on the first access, and one
wait state on burst accesses. The performance of this system is more than
85% of the maximum! One cannot do that with a generic RISC.

Jonathan