🚀 go-pugleaf

In article <26716@amdcad.AMD.COM> tim@amd.com (Tim Olson) writes:
>Well, from the previous postings and email conversations, it appears
>that nearly every RISC processor besides the Am29000 has a restriction
>on what can go in a branch delay slot, including SPARC, MIPS, 88000,
>i860, and ROMP.  Most of the restrictions are advisory (don't do this; the
>result is undefined), but the ROMP has hardware to detect and trap this
>condition.
>
>One interesting thing to think about if control transfers are allowed in
>branch delay slots is how a delay-slot call should work:

I missed the beginning of all this but I thought this might be interesting.

The Stanford MIPS-X processor has a branch/jump delay of 2.  The new
PC is computed by adding the offset to the value of the current PC when
the instruction reaches its ALU stage.  The pipeline is: IF RF ALU MEM WB.
So for the following:

	0	br offset=5
	1	nop (delay slot 1)
	2	nop (delay slot 2)
	3	...
	...
	7	nop (br destination)

the sequence would be 0, 1, 2, 7.

Now consider this interesting loop:

	0	nop
	1	nop
	2	nop
	3	br offset=-1
	4	br offset=-1
	5	br offset=-1
	6	nop
	7	nop

The sequence of the PC is 0, 1, 2, 3, 4, 5, 4, 3, 2, 1, 0, 1, 2, 3, ...

One morning I walked in and I saw someone running the simulator with
the PC running backwards!  This worried me because I had designed the PC,
and had never expected that it could `increment' backwards...

On the question of calls in delay slots, MIPS-X does the same as Tim explains
for the Am29000, except that there are two delay slots.

Paul Chow
Dept. of Electrical Engineering
University of Toronto

pc@eecg.toronto.edu