🚀 go-pugleaf

In article <407@bnr-fos.UUCP> schow@leibniz.uucp (Stanley Chow) writes:
>In a recent series of articles about address modes and other topics,
>some posters claim that memory bandwidth is not a problem - to quote
>Brian Case, "bandwidth can be had in abundance". I happen to think that
>we do not enough bandwidth now. What to other people think?
>  ...
>    It seems people can already build cores that are faster than the
>    on-chip cache. One can always throw silicon at a multiplier to make
>    it faster (I know, there are limits with loading, ..).

You can always improve bandwidth with silicon (and wires).  To double
bandwidth, double the data bus size.  You can also use interleave or
special chip modes (static column or page mode access) to improve
bandwidth.

As I remember, Brian Case's statement was indeed referring to
bandwidth.

On the other hand, latency (roughly the number of cycles to get the
data after you figure out its address), is a much more difficult
problem.  Making the latency twice as good (50% as long) can be very
tough.  Some latency's are not possible with current technology ( 1 ns
latency for a 1 Megaword system for example).  Can you rephrase your
questions to discriminate between bandwidth and latency?

Thanks - Mark (davis@cs.unc.edu or uunet!mcnc!davis)