🚀 go-pugleaf

Does anyone know how long the integer multiply and divide instructions take
on the MIPS R2000?  Kane's book has examples in which the the MFLO to
retrieve the result be issued at least 11 cycles after the MULT.  Other
examples say 12.  For the divide, there is no indication anywhere.  

Also, why is there a 2-cycle delay between a MFLO and a subsequent MULT,
while there is no delay between the MFLO r5 and an ADD r6,r5,r4?  For the
latter to be true the value has to be available (extracted from LO) at
the end of MFLO's ALU cycle.  If the mult were issued on this same cycle
(i.e. with a 1-cycle delay), it seems as if it could not affect the
extracted value, even if an interrupt occurred.  Thanks very much.

	-- Dave Bradlee
	   University of Washington