Article View: comp.arch
Article #20777Re: One aspect of bandwidth (backplane bus)
From: John Mashey
Date: Sat, 15 Apr 1989 20:21
Date: Sat, 15 Apr 1989 20:21
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3120 bytes
In article <17500@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
.....
>Seems to me that backplanes (or, in general terms, processor-to-
>main-storage data trunks) are nearly pooped out. At least for the
>kinds of air cooled, medium-priced computers that tend to have
>microprocessors for CPUs.
....
>And that's just for the very next generation of air cooled, medium
>priced CPU --- 60 VUP performance is eminently forseeable in the next
>6 to 24 months (schedule varies depending upon who you talk to :-).
>Soon thereafter it will be 1994, when you can buy 125-250 VUP micros
>for cheap, and when the few remaining software issues concerning
>32-way multiprocessors will be solved :-).
There's a issue of UNIX Review coming up a while off on something
like "fundamental systems technologies". We (the editorial board, that is)
were discussing this issue, which might tentatively 3 articles, looking at
thetechnologies over the next few years:
1. CPUs (great! mips/flops are almost free)
2. Busses (oh, oh! we're in trouble trying to match the CPUs)
3. I/O (esp. disks) (well, now we're REALLY in trouble).
A particularly interesting issue about busses: MultiBus, and especially,
VMEBUS, happened about the same time as micros to which they were matched.
VMEBUS had enough headroom to remain adequate, even for a 20-VUPS machine
(albeit barely, as an I/O bus). This was good, because it let people
leverage off many other people's controller development. (Remeber that
a VMEBUS is something like 40MB peak, 25MB sustained).
As Mark notes, the coming 100+ VUP micros aren't so forgiving.
1) In a balanced system, a single VMEBUS (with block-mode controllers,
appropriately interleaved/fifoed memory controllers, etc) is out of gas
for anything above a 20-25-VUPS system, for sure.
2) Maybe no one will expect to have a "standard" memory bus of any sort,
and instead, just connect up controllers to I/O adaptors.
This is sort of sad.
3) it is pretty easy to look ahead just a few years, to see how to build
systems in the 500-1000-VUPS range, which could fit in a deskside (large
deskside) package, if you wanted, assuming you could build a main
memory bus in the 750-1500MB/sec region......
4) Does anybody know of anything like that being proposed as a standard?
No? well, it looks like we're in for a lot more multiple-bus architectures...:-)
--
-john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!decwrl!pyramid!prls!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: One aspect of bandwidth (backplane bus) Message-ID: <17527@winchester.mips.COM> Date: 15 Apr 89 20:21:13 GMT References: <407@bnr-fos.UUCP> <17500@obiwan.mips.COM> Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 53