🚀 go-pugleaf

Thanks to all of those that sent me mail about the CDC 8600. I
received plenty of responses, and was eventually pointed in the
direction of someone who actually worked on the machine with Seymour
Cray. So to sum up, here is what I have:
 
The CDC 8600 was a follow on to the 7600, but not like the 7600 was a
follow on to the 6600. The 8600 was different in several ways. It had
4 CPU's running at 8 nanoseconds with 250 Kwords of memory (20 bit
address space). Two types of memory were designed. Core memory with
about 20 nanoseconds access time. Semiconductor memory with about 22
nanoseconds access time.
 
The modules had discrete transistors, 18 boards/module, 4 layer
boards. 13 modules/CPU. Approximate speed was 2.5 x 7600 speed/CPU.
Total speed was about 10 x 7600 speed.
 
It also had a 64 bit word, not 60, which was another departure from
the 6600/7600. It used ones complement arithmetic with 2 sign bits, 14
bit exponents and a 48 bit coefficient.
 
There were no vector registers. It had 16 general purpose registers.
 
Operation speed: (in clock periods)
 
        Boolean         2
        shift           3
        long add        3
        multiply        8
        floating add    8
        read            15
        write           1
        branch in stack 7
          fall through  3
          out of stack  15
 
The 8600 project was terminated due to financial problems in CDC.
Also, the Cray-1 was not an 8600. It did evolve from the 8600 though.
It also had ideas taken from the Star 100, such as vector registers. 
(this was stated by Seymour at Supercomputing 88)


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Michael Tighe
internet: mjt@super.org
   uunet: ...!uunet!super!mjt