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Article #20792Re: The IPI fast peripheral interface
From: Anonymous Author
Date: Wed, 19 Apr 1989 15:23
Date: Wed, 19 Apr 1989 15:23
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/ hpcupt1:comp.arch / Anonymous@hpcupt1.HP.COM (Anonymous Author) / 8:23 am Apr 19, 1989 / A good explanation is in the April 13, 1989 issue of Electronic Design, pp 129-132. IPI is a four-layer ANSI interface. You will see IPI-1 (state machine and procedures for device selection), IPI-2 (device-level interface), and IPI-3 (supplies the device-generic I/O bus interface). IPI-0 is a 16-bit parallel bus running at 5 MHz implemented in a variety of ways. Joe Martinka Hewlett-Packard ----------
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!utstat!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!rutgers!ucsd!sdcsvax!ucsdhub!hp-sdd!hplabs!hpda!hpcupt1!Anonymous From: Anonymous@hpcupt1.HP.COM (Anonymous Author) Newsgroups: comp.arch Subject: Re: The IPI fast peripheral interface Message-ID: <6310016@hpcupt1.HP.COM> Date: 19 Apr 89 15:23:27 GMT References: <12478@reed.UUCP> Organization: Hewlett Packard, Cupertino Lines: 14