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Article #20808Re: One aspect of bandwidth (backplane bus)
From: Brian bcase Case
Date: Sun, 16 Apr 1989 17:55
Date: Sun, 16 Apr 1989 17:55
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1370 bytes
>2) Maybe no one will expect to have a "standard" memory bus of any sort, >and instead, just connect up controllers to I/O adaptors. >This is sort of sad. But very necessary. At very high rates, it just doesn't make sense for small-medium sized computers to connect to memory over a "bus" (unless that bus is ECL, 32 to 64 bytes wide, 8 transfers per transaction (needed to recover from the latency), 20ns per transfer (bandwidth: 1.6 to 3.2 Gbytes/sec). Using current DRAM technology, the array size needed to implement this requires much space and the minimum memory size is huge. With next generation DRAM technology, the min. size is even bigger!!). Though it's done for different reasons, Macintosh is a sign of times to come: all the (high-speed) main memory is "special," and is right next to the CPU/cache. What do you do for multiprocessors? Build that ECL bus and charge several $million.
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Path: arc1-ca.pugleaf.net!utzoo!dptcdc!jarvis.csri.toronto.edu!mailrus!purdue!decwrl!sun!pitstop!sundc!seismo!uunet!portal!cup.portal.com!bcase From: bcase@cup.portal.com (Brian bcase Case) Newsgroups: comp.arch Subject: Re: One aspect of bandwidth (backplane bus) Message-ID: <17298@cup.portal.com> Date: 16 Apr 89 17:55:00 GMT References: <407@bnr-fos.UUCP> <17500@obiwan.mips.COM> <17527@winchester.mips.COM> Organization: The Portal System (TM) Lines: 15