🚀 go-pugleaf

In article <4101@tolerant.UUCP> rob@tolerant.UUCP (Rob Kleinschmidt) writes:
| Once in a while, the atomic nature of a complex instruction can have
| real advantages over a sequence of fast single cycle instructions.
| Because the complex instruction cannot be interrupted in mid sequence,
| there is no need to modify processor priority. This can allow better
| manipulation of shared data items (linked lists, counters, etc.)
| especially by user level processes. Anybody got a good way for a user
| execute an un-interupted sequence of a dozen RISC instructions ?


I believe the i860 has a Lock bit which can be set by the user,
disabling interrupts and setting an external Lock pin.  It is tracked by
a watchdog timer, so that after a certain number of cycles (10?) it
automatically is reset (to prevent the user from disabling interrupts
for too long).

On the Am29000, the on-chip timer is disabled separately from the
external interrupts.  Thus, an operating system could supply a
user-invokable disable() routine which masked interrupts and set the timer
to interrupt in a small number of cycles.  The user can then perform a
series of operations, then call an enable() routine (resetting the timer
and the interrupt mask).  If enable() were not called in time, the timer
would catch it and force the interrupt mask off.

One other (software) method is to associate a semaphore with each
critical region (or a collection of critical regions), and manipulate it
with an atomic load/set instruction (which many RISC processors have). 
Interrupts don't have to be disabled if all users of the critical region
obey the semaphore.  I guess one may then have to worry about deadlock
conditions, though...

	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)