Article View: comp.arch
Article #20860Z80 has no interruptible instructions (was Re: Complex Instructions)
From: Andrew Klossner
Date: Fri, 21 Apr 1989 16:38
Date: Fri, 21 Apr 1989 16:38
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[This is really just nit picking.]
"The Z80 will handle interrupts inside of block moves ..."
This isn't really the case.
The way that the Z80 block move (is it spelled LDIR?) instruction works is:
-- move one byte from here to there
-- decrement the PC
Yep, it refetches the instruction for each byte.
It looks like a long interruptible instruction, but it's actually a
self-looping non-interruptible instruction.
A good example of an interruptible instruction is block transfer
("BLT") on the PDP-10. Its three operands are initial source address,
initial destination address, and one of the end addresses. The initial
addresses are stored in the two halves of a register. If an interrupt
happens, the register is updated so that the two addresses indicate
where to resume, and the saved PC points to the BLT.
[Now somebody will pop my bubble and tell me the PDP-10 used the Z80
self-looping hack ...]
-=- Andrew Klossner (uunet!tektronix!orca!frip!andrew) [UUCP]
(andrew%frip.wv.tek.com@relay.cs.net) [ARPA]
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!pasteur!ames!lll-winken!uunet!tektronix!orca!tekecs!frip!andrew From: andrew@frip.wv.tek.com (Andrew Klossner) Newsgroups: comp.arch Subject: Z80 has no interruptible instructions (was Re: Complex Instructions) Message-ID: <11320@tekecs.GWD.TEK.COM> Date: 21 Apr 89 16:38:10 GMT References: <57252@yale-celray.yale.UUCP> <4101@tolerant.UUCP> <134@dg.dg.com> Sender: andrew@tekecs.GWD.TEK.COM Organization: Tektronix, Wilsonville, Oregon Lines: 26