🚀 go-pugleaf

In article <100524@sun.Eng.Sun.COM>, dgh%dgh@Sun.COM (David Hough) writes:

   > I have heard that adder carry propagate time and multiplier array
   > size are the key constraints with a floating-point chip; ....

Well, only true for those chips which don't have an explicit hardware
divide unit, e.g. Clipper, Intel 860, TI 8847, Moto 88K, Transputer.
These folks use the multiply and the add hardware, plus a Newton-Rhapson
iterative algorithm, to synthesize division.  Other FP chips have a
separate functional unit for divides (allowing a divide to be overlapped
with a multiply & an add).  I believe HP Precision, Weitek, and MIPS
have FP chips with divider hardware.  The divider can indeed become the
critical path of the FP unit.

   > ... Memory bandwidth tends to
   > be the key constraint on overall system performance unless
   > floating-point division and sqrt dominate.  The last describes
   > a minority of programs but they are quite important in some
   > influential circles.

As David has said before on this forum, the circuit simulator SPICE
executes a very large number of divides and square roots.  To VLSI
designers (like the ones who design FP chips!), SPICE is quite an
important program.  Hint: look at the equations for the pinchoff
voltage of a field effect transistor (such as the MOSFETs in CMOS
technology).  Count the number of divides and square roots.
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
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