🚀 go-pugleaf

In article <18201@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
| In article <3975@mipos3.intel.com> kds@blabla.UUCP (Ken Shoemaker) writes:
| >....  On the i486, on the other hand, you don't get load delay
| >slots, and you don't get deferred branches.  You also get a two stage
| >instruction decode.  This means that you can run the memory cycle one clock
| >earlier with respect to the execution stage in the pipeline than you can on
| >most risc machines because the execution stage is one clock later in the
| >pipeline.  Thus no load delay slot.  This also means that you take another 
| >clock on branches taken, which is why a branch taken on the i486 requires 
| >3 clocks, whereas on most risc machines it takes 2 clocks (the second 
| >being the branch delay slot).  We think that this is a good tradeoff, since
| >we need the extra clock to decode the instructions anyway....
|
| Yes, certainly a good tradeoff; loads are more frequent than branches.

Interesting -- what kind of numbers do you see?  On the Am29000, we tend
to see just the opposite, although they are somewhat close:

--- compress (loads > branches) ---
          0.36% Calls
         12.51% Jumps
         16.17% Loads
          9.29% Stores

--- dhrystone 1.1 ---
          2.84% Calls
         13.97% Jumps
         13.76% Loads

--- diff ---
          0.34% Calls
         17.50% Jumps
         15.44% Loads
          6.31% Stores

--- grep ---
          1.13% Calls
         15.07% Jumps
         13.57% Loads
         3.04% Stores

--- nroff ---
         1.86% Calls
         15.65% Jumps
         10.73% Loads
          3.73% Stores

--- 29k assembler ---
          1.58% Calls
         19.21% Jumps
         10.95% Loads
          6.14% Stores


	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)