🚀 go-pugleaf

In article <25423@amdcad.AMD.COM> rpw3@amdcad.UUCP (Rob Warnock) writes:
>
>You can also make a two-stage synchronizer, where the second stage can
>fail only if the first stage comes out of metastable just as the second
>stage clocks. [You have to bias the output of the first stage so a first-
>stage metastable looks like a clean one or zero to the second stage.]
>Depending on your environment, this is sometimes better than clocking
>a single-stage synchronizer at 1/2 the rate.
>

I believe that Digital used to take all 74S74 parts (back when
they were an important part of real CPUs) and run a very precise
test on (Tsetup + Thold) - the actual length "window" surrounding
the positive going clock edge during which data had to be stable
in order to get a clean "1" on Q in a guaranteed (short) time.

Real parts were quite variable with respect to this parameter.
(The spec for the 74S74 is 3ns setup, 2ns hold from my TTL data book -
supposedly they found that some parts were three orders of magnitude
better, in the area of a few picoseconds).  The ones that were
particularly good were given a special part number and were then
used a the second stage of the circuit described above.  This
served as a practical engineering approach to minimizing the
failure rate.

What do current VLSI designers do to minimize the likelyhood of
metastable failure?

-- 
Jeff Berkowitz N6QOM			uunet!sequent!jjb
Sequent Computer Systems		Custom Systems Group